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INTEGRATED CIRCUITS
DATA SHEET
SAA7348GP All Compact Disc Engine (ACE)
Preliminary specification File under Integrated Circuits, IC22 1997 Jul 11
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.4 7.5 7.5.1 7.6 7.7 7.7.1 7.8 7.8.1 7.9 7.10 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.1.11 8.1.12 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog front-end Decoder front-end Servo front end Decoder functions Servo functions Signal conditioning Focus control Radial control Off-track counting Off-track detection Shock detection Defect detection Driver interface Laser interface Subcode interface Digital output Format S2B interface Audio support Serial audio data interface CD-ROM support Serial CD-ROM data interface Reset External ROM support MICROCONTROLLER INTERFACE Microcontroller applications registers CLK generate register (CLKgen) Port Servo Register (PSR) Servo Control Register (SCR) Servo Status Register (STR) Motor Output QCLV Register (MOQ; address 0XF2H and 0XF3H) P3 Register Decoder Status Register (DSR) Motor Setpoint Register (MSR; address 0XF9H) Motor Gain QCLV Register (address 0XFAH) Data Direction Registers (DDR0, DDR2 and DDR3) Configuration Control Register (CCR) A second serial interface 2 8.1.13 8.1.14 8.1.15 8.2 8.3 8.4 8.4.1 9 10 10.1 10.2 10.3 11 12 12.1 12.2 12.3 12.4 13 14
SAA7348GP
Memory map access to the servo PLL Registers DIV17 Register (address 0X9FH) Memory map Summary of the functions controlled by decoder registers 0 to F Summary of servo commands Summary of servo command parameters LIMITING VALUES CHARACTERISTICS General characteristics Subcode interface timing characteristics I2S timing characteristics PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
1997 Jul 11
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
1 FEATURES
SAA7348GP
* Improved playability on ABEX TCD-721R, TCD-725 and TCD-714 discs * Automatic closed loop gain control available for focus and radial loops * On chip clock multiplier allows the use of 8.4672 MHz crystal * S2B serial interface with host controller * Double speed servo * Integrated engine controller (high speed embedded 80C51) * External program support. 2 GENERAL DESCRIPTION
* Focus servo loop * Radial servo loop * Built-in access procedure with fast track count possibilities * Sledge motor servo loop with pulsed sledge support * High speed error correction, up to sixteen times over-speed * Supports three different over-speed ranges with only one external crystal * Lock-to-disc mode * Full turntable motor control * Full error correction strategy, t = 2 and e = 4 * All standard decoder functions implemented digitally * Adaptive digital HF equalizer * FIFO overflow concealment for rotational shock resistance * Digital audio interface (EBU), audio and data * 2 and 4 times oversampling integrated digital filter, including fs mode * Audio data peak level detection * Kill interface for DAC deactivation during digital silence * All TDA1301 (DSIC2) digital servo functions * Low focus noise 3 ORDERING INFORMATION
The SAA7348 All Compact Disc Engine (ACE) combines the functionality of a CD decoder (LO9585), a digital servo (OQ8868) and a microcontroller core (80C51 based) on a single chip. It was developed for high speed CD-ROM applications but, due to the large scale integration, can also be used in other CD applications. The internal microcontroller makes it possible to develop other applications quickly. The microcontroller can operate with internal or external ROM. Additional features include: * High level integration * Improved communication speed.
PACKAG0E TYPE NUMBER NAME SAA7348GP DESCRIPTION VERSION SOT407-1 LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
1997 Jul 11
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
4 QUICK REFERENCE DATA SYMBOL VDDD(pads) VDDD(core) VDDA IDD fxtal Tamb Tstg Note PARAMETER digital supply voltage for pad cells digital supply voltage for the core analog supply voltage supply current crystal frequency operating ambient temperature storage temperature note 1 note 1 n = 8 mode CONDITIONS MIN. 4.5 3.0 3.0 - 8 0 -55
SAA7348GP
TYP. 5.0 3.3 3.3 90 8.4672 - -
MAX. 5.5 3.6 3.6 - 35 70 +125
UNIT V V V mA MHz C C
1. The analog and digital core supply pins (VDDA and VDDD(core)) must be connected to the same external supply. The core and pads can operate at different voltages and should never be connected together directly.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
5 BLOCK DIAGRAM
VSSA VDDA 2
(1)
SAA7348GP
handbook, full pagewidth
VSSD
SBSY
RCK SUB 94 95
VALID DAC 65
DATA
SCLK
KILL DEEM 97 96 89 71 DOBM SUBQW MOTOV MOTOS FB C2FAIL CFLG
VDDD(core) VDDD(pads) 2 2 9 3
(2) (3) (4) (5)
SFSY 92 93
WCLK 67 68
DACCLK 69 62
66
MIDLAD REFLCA HFIN REFHCA Iref
7 8 9 10 11 86 85 HF FRONT-END DECODER 91 73 72
SAA7348GP
84 VRH D1 D2 D3 D4 S1 S2 IrefT FTCH FTCL 14 15 16 17 20 21 22 23 LF FRONT-END 78 DIGITAL SERVO 79 80 90 24 25 98 99 100 83 82 74 75 FOK TL RP DSDEN CLO RA FO SL OTD DEFI DEFO LDON
XTALI XTALO SELPLL
28 27 26 CLOCK PLL 80C51 5 6
TPWM TEN
TEST 8 1 (1) (2) (3) (4) 2 3 30 31 32 33 34 35 36 37 40 to 47 8 53 to 60 48 49 50
Pins 13 and 19. TS1 TS3 Pins 12 and 18. TS2 Pins 39 and 88. Pins 29, 38, 51, 61, 63, 70, 76, 81 and 87. (5) Pins 52, 64 and 77.
RXD0
INT0 INT1
RXD1 TXD1
WR RD
TXD0
A8 to A15
AD0 to AD7
ALE PSEN EA
MGK498
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
6 PINNING SYMBOL TS1 TS2 TS3 RST TPWM TEN MIDLAD REFLCA HFIN REFHCA Iref VSSA1 VDDA1 VRH D1 D2 D3 VSSA2 VDDA2 D4 S1 S2 IrefT FTCH FTCL SELPLL XTALO XTALI VSSD1 RXD0 TXD0 INT0 INT1 RXD1 TXD1 WR RD VSSD2 VDDD1(core) A8 1997 Jul 11 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TYPE(1) I I I I O O A A A A A S S A A A A S S A A A A A A I A A S B B B B B B B B S S B DESCRIPTION test control input; this pin should be tied LOW test control input; this pin should be tied LOW test control input; this pin should be tied LOW power-on reset input tray PWM output tray enable output ladder middle decoupling of High Frequency (HF) ADC ladder low decoupling of HF ADC HF input ladder high decoupling of HF ADC reference current input analog ground 1 for HF front-end analog supply voltage 1 for HF front-end (3.3 V) calibrated reference voltage output from ADC unipolar current input (central diode signal input) unipolar current input (central diode signal input) unipolar current input (central diode signal input) analog ground 2 for LF front-end analog supply voltage 2 for LF front-end (3.3 V) unipolar current input (central diode signal input) unipolar current input (satellite diode signal input) unipolar current input (satellite diode signal input) current reference, for input range of LF front-end ADCs fast track counter comparator (+) input fast track counter comparator (-) input enables internal clock multiplier PLL crystal output crystal input digital ground 1 P3.0 P3.1 P3.2 (interrupt 0) P3.3 (interrupt 1) P3.4 P3.5 P3.6; active LOW P3.7; active LOW digital ground 2 digital supply voltage 1 for the core (3.3 V) P2.0 (address or I/O) 6
SAA7348GP
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
SYMBOL A9 A10 A11 A12 A13 A14 A15 PSEN ALE EA VSSD3 VDDD1(pads) AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSSD4 DACCLK VSSD5 VDDD2(pads) VALID DAC DATA WCLK SCLK VSSD6 SUBQW MOTOS MOTOV DSDEN CLO VSSD7 VDDD3(pads) RA FO SL VSSD8 1997 Jul 11
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
TYPE(1) B B B B B B B B B B S S B B B B B B B B S T S S T T T T T S O T T O O S S T T T S P2.1 (address or I/O) P2.2 (address or I/O) P2.3 (address or I/O) P2.4 (address or I/O) P2.5 (address or I/O) P2.6 (address or I/O) P2.7 (address or I/O)
DESCRIPTION
program store enable (pull-up; active LOW) address latch enable (pull-up) external ROM select (active LOW); enhanced hooks digital ground 3 digital supply voltage 1 for the pads (5 V); pins 26 to 60 P0.0 (data, address or I/O) P0.1 (data, address or I/O) P0.2 (data, address or I/O) P0.3 (data, address or I/O) P0.4 (data, address or I/O) P0.5 (data, address or I/O) P0.6 (data, address or I/O) P0.7 (data, address or I/O) digital ground 4 BCC-DAC clock output digital ground 5 digital supply voltage 2 (level shifter) for the pads (5 V) data validity flag; C2 error flag; (3-state) serial audio data output to DAC (3-state) serial data output to block decoder (3-state) word clock output (3-state) serial bit clock output (3-state) digital ground 6 subcode output; Q to W subcode bits motor output, sign motor output, value DSD enable output (active LOW) clock output digital ground 7 digital supply voltage 3 for the pads (5 V); pins 1 to 6 and 65 to 100 radial actuator output focus actuator output sledge control output digital ground 8 7
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
SYMBOL RP TL FOK CFLG C2FAIL VSSD9 VDDD2(core) DOBM OTD FB SBSY SFSY RCK SUB DEEM KILL DEFI DEFO LDON Note
PIN 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
TYPE(1) OD OD OD OD OD S S T O OD T T I T O OD I O OD track loss signal (open drain)
DESCRIPTION radial polarity signal (open drain) focus OK signal or decoder measurement signal (open drain) correction flag output (open drain) indication of correction failure (open drain) digital ground 9 digital supply voltage 2 for the core (3.3 V) EBU bi-phase mark output (externally buffered) (3-state) off-track detect FIFO boundary, motor overflow (open drain) subcode block sync (3-state) subcode frame sync (3-state) subcode clock input P to W subcode bits (3-state) deemphasis active output kill output (open drain) defect detector input defect detector output laser drive on output (open drain)
1. Pin type abbreviations: O = Output, I = Input, S = power Supply, A = Analog function, OD = Open Drain, B = Bidirectional, T = 3-state output. All supply pins must be connected directly to their respective external power supply voltages.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
handbook, full pagewidth
77 VDDD3(pads)
88 VDDD2(core) 87 VSSD9
100 LDON
TS1 TS2 TS3 RST TPWM TEN MIDLAD REFLCA HFIN
76 VSSD7 75 CLO 74 DSDEN 73 MOTOV 72 MOTOS 71 SUBQW 70 VSSD6 69 SCLK 68 WCLK 67 DATA 66 DAC 65 VALID 64 VDDD2(pads) 63 VSSD5 62 DACCLK 61 VSSD4 60 AD7 59 AD6 58 AD5 57 AD4 56 AD3 55 AD2 54 AD1 53 AD0 52 VDDD1(pads) 51 VSSD3 EA 50
86 C2FAIL
81 VSSD8 80 SL
89 DOBM
96 DEEM
99 DEFO
92 SBSY
85 CFLG
93 SFSY
98 DEFI
94 RCK
90 OTD
97 KILL
95 SUB
84 FOK
1 2 3 4 5 6 7 8 9
REFHCA 10 Iref 11 VSSA1 12 VDDA1 13 VRH 14 D1 15 D2 16 D3 17 VSSA2 18 VDDA2 19 D4 20 S1 21 S2 22 IrefT 23 FTCH 24 FTCL 25 SELPLL 26 XTALO 27 XTALI 28 VSSD1 29 RXD0 30 TXD0 31 INT0 32 INT1 33 RXD1 34 TXD1 35 WR 36 RD 37 VSSD2 38 VDDD1(core) 39 A8 40 A9 41 A10 42 A11 43 A12 44 A13 45 A14 46 A15 47 PSEN 48 ALE 49
SAA7348GP
78 RA
79 FO
82 RP
91 FB
83 TL
MGK497
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
7 FUNCTIONAL DESCRIPTION
SAA7348GP
data as incorrect. The off-track input is connected internally to the servo section.
The ACE combines the functionality of a DSICS (OQ8868), a CD65 (LO9585) and an 80C51-based microcontroller (83C654). In addition, a large part of the glue logic has been integrated to help minimize the number of external components required in CD-ROM applications. 7.1 Analog front-end
handbook, halfpage
+3.3 V 820 820
VDDA1
13
The front-end circuit can be split into two parts: 1. The decoder input (HF front-end) 2. The servo input (LF front-end). Each is powered by a separate power supply pin pair.
MIDLAD 10 nF 820 VSSA1
7
12
MGK500
7.1.1
DECODER FRONT-END
The EFM signal is fed to the decoder through an ADC, which is preceded by an AGC stage. In order to make full use of the digital front-end resolution, the gain control amplifier should deliver a constant 1.4 V p-p output signal. The gain range of the AGC is 16 dB and is controlled in steps of 1.0 dB. The gain of the variable gain amplifier is controlled by an on-chip digital gain control block. This block allows for both automatic and microcontroller gain control. The internal HF detector is sensitive to any disturbance on the HF signal; a clean (good signal-to-noise ratio) EFM signal is necessary since high frequency components can disturb the HF detector. The input range of the HF front-end varies from 2.3 V p-p down to 0.35 V p-p. If in the lower range the signal level is between 25% and 75% of the ADC range, the HF detector will signal NO HF (In this range an ADC LSB translates into 5.5 mV, so half the range equals 175 mV. If the total offset was equal to 6 LSBs, the signal range would be reduced by 2 x 33 mV. In this case a signal of less than 109 mV would signal NO HF). To ensure the AGC offset is minimized when the AGC gain is high, it is necessary to connect a resistor divider to MIDLAD, as shown in Fig.3. The SAA7348 contains an on-chip digital equalizer and data slicer. The equalizer is adaptive; actual equalization depends on the disc speed. The data slicer has a microcontroller programmable bandwidth. A fully digital internal PLL is used to regenerate the bit clock. The bandwidth and equalization of the PLL can be programmed by the microcontroller. An off-track input is necessary for certain applications. If the off-track input flag is HIGH, the SAA7348 will assume that the servo is following on the wrong track, and will flag all incoming HF
Fig.3 Front-end offset compensation.
7.1.2
SERVO FRONT END
The servo front end contains six current-input ADCs (four for focus and two for the radial signals). The ADCs do not require external capacitors, unlike the OQ8868 or CD7 (SAA7370). For high performance radial access, a comparator input is available for the FTC (Fast Track Count) signal. The dynamic range of the ADC input currents can be adjusted over a range dependent on the value of an external resistor connected to IrefT. The maximum input current for the central and satellite diodes, respectively, is given below: 2.4 x 10 I i(central) ( max ) = ----------------------- ( A ) R IrefT I i ( satellite )
( max ) 6
1.2 x 10 = ----------------------- ( A ) R IrefT
6
VRH is generated internally. The value of VRH is dependent upon the spread of internal capacitors and on the value of the reference current generated by the external resistor on IrefT. Typical input currents for a range of resistance values are given in Table 1.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
Table 1 Typical input currents for a range of values of RIrefT TYPICAL CURRENT INPUT RANGE RIrefT (k) fsys D1, D2, D3, D4 (A) 12.000 10.909 10.000 8.889 8.000 7.273 6.667 6.154 5.581 5.106 4.706 4.286 3.871 3.529 3.200
(1)
SAA7348GP
= 4.2336 MHz S1, S2 (A) 6.000 5.455 5.000 4.444 4.000 3.636 3.333 3.077 2.791 2.553 2.353 2.143 1.935 1.765 1.600 VRH (V) 1.891 1.719 1.576 1.396 1.261 1.146 1.051 0.970 0.880 0.805 0.742 0.675 0.610 0.556 0.504
fsys(1) = 8.4672 MHz D1, D2, D3, D4 (A) 12.000 10.909 10.000 8.889 8.000 7.273 6.667 6.350 - - - - - - - S1, S2 (A) 6.000 5.455 5.000 4.444 4.000 3.636 3.333 3.175 - - - - - - - VRH (V) 0.946 0.860 0.788 0.698 0.631 0.573 0.526 0.500 - - - - - - -
200 220 240 270 300 330 360 390 430 470 510 560 620 680 750 Note
servo clock 1. fsys is always equal to ------------------------------ ; see Table 9. 2 The preset latch command can be used to select this method of VRH automatic adjustment. Alternatively, the dynamic range of the input currents can be made dependent on the ADC reference voltage, VRH. In this case, the maximum input current for the central and satellite diodes, respectively, is: I i(central) ( max ) = f sys x V RH x 1.10 x 10
-6
playback speeds can be selected, depending on the crystal frequency and the internal clock settings; see Table 2. The following functions are performed in the decoder block: * Demodulation (includes sync protection circuit); converts the 14-bit EFM data and subcode words into 8-bit symbols. * Subcode data processing. * Error correction; a t = 2, e = 4 type is used on both C1 (32 symbol) and C2 (28 symbol) frames. The error corrector can correct up to 2 errors on the C1 level and up to 4 errors on the C2 level. The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags that are used by C2. The C2 output flags are used by the interpolator to conceal uncorrectable errors for audio output; they are also output via the EBU signal (DOBM) and the VALID output with I2S for CD-ROM applications.
( A ) ( A )
I i(satellite) ( max ) = f sys x V RH x 0.55 x 10 where fsys = 4.2336 MHz.
-6
VRH can be set to any one of 32 pre-defined levels, selectable under software control. VRH is initially set to 2.5 V using the preset latch command, then incremented or decremented one level at a time by repeatedly resending the same commend. 7.2 Decoder functions
The SAA7348 is a multi-speed decoding device with an internal phase locked loop clock multiplier. Several 1997 Jul 11 11
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
* Motor control; the spindle motor is controlled by a fully integrated digital servo. Address information from the internal 8 frame FIFO and disc speed information are used to calculate the motor control output signals. Several output modes are supported: - Pulse density, 2-line (true complement output), 1 x n MHz sample frequency Table 2 Decoder playback speeds; note 1 INTERNAL FREQUENCY (MHz) REGISTER B 00XX 00XX 01XX 01XX 10XX 10XX 11XX Notes 1. X = don't care. REGISTER E 0XXX 1XXX 0XXX 1XXX 0XXX 1XXX 0XXX 67.7376(2) n=2 n=8 - - n=4 n = 16 - 50.8032(2) n = 1.5 n=6 - - n=3 n = 12 - 33.8688(2)(3) n=1 n=4 - - n=2 n=8 -
SAA7348GP
- PWM-output, 2-line, 22.05 x n kHz modulation frequency - CDV motor mode - Brushless motor control mode. A simplified illustration of the data flow through the decoder is shown in Fig.4.
16.9344(4) - n=2 n=1 n=4 - - n=2
2. With an 8.4672 MHz crystal, and only if SELPLL = 1 (i.e. clock multiplier enabled; see also Section 8.1.1). 3. Can use external 33.8688 MHz crystal. 4. Can use external 16.9344 MHz crystal.
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1997 Jul 11
handbook, full pagewidth
1 0 RCK SUBQW 0 : reg D = xx0x CD GRAPHICS INTERFACE SUBCODE INTERFACE reg F EBU INTERFACE DOBM MICROCONTROLLER INTERFACE SBSY SFSY SUB
Philips Semiconductors
0 : reg D = xx10 1 : reg D = xx11
SUBCODE PROCESSOR
EFM 0 : reg A = xx0x 1 : reg A = xx1x 1 : reg 3 = xx10 (1fs mode) reg A reg E
All Compact Disc Engine (ACE)
DIGITAL PLL AND DEMODULATOR
FIFO 1
0
0 : no pre-emphasis detected OR reg D = 0xxx 1 : pre-emphasis detected AND reg D = 1xxx registers 3, 7 and E
13
1 1 0 0 1 1 0 FADE/MUTE/ INTERPOLATE 0 DIGITAL FILTER PHASE COMPENSATION reg 3 DE-EMPHASIS FILTER 1 0 0 KILL KILL 0 : reg 0 = x000/reg 3 = 101x/reg 7 = 00xx/reg E = x0xx
MGK499
ERROR CORRECTOR
DAC 1 0 I2S-BUS INTERFACE DATA SCLK WCLK 0 : reg 3 = 101x (CD-ROM modes)
MONO FUNCTION
1 : reg 7 = 11xx or 00xx
reg 3 VALID 1 0 1 0 DEEM
reg 7
1 : pre-emphasis detected AND reg D = 0xxx OR reg D = 11xx
Preliminary specification
SAA7348GP
Fig.4 SAA7348 decoder function: simplified data flow.
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
7.3 7.3.1 Servo functions SIGNAL CONDITIONING
SAA7348GP
The radial or tracking error signal is generated by the satellite detector signals R1 and R2. The radial error signal can be formulated as follows: REs = (R1 - R2) x re_gain + (R1 - R2) x re_offset where the index `s' indicates the automatic scaling operation performed on the radial error signal. This scaling is necessary to avoid non-optimal dynamic range usage in the digital representation and to reduce the radial bandwidth spread. Furthermore, the radial error signal will be free of offset during disc start-up. The four signals from the central aperture detectors, together with the satellite detector signals, generate a track position signal (TPI), which can be formulated as follows: TPI = sign [(D1 + D2 + D3 + D4) - (R1 + R2) x sum_gain] where the weighting factor sum_gain is generated internally by the SAA7348 during initialization.
The digital codes retrieved from the ADCs are applied to logic circuitry to obtain various control signals. The signals from the central aperture diodes are processed to obtain a normalised focus error signal: D1 - D2 D3 - D4 FE n = --------------------- - --------------------D1 + D2 D3 + D4 where the detector set-up illustrated in Fig.5 is assumed. For single Foucault focusing, signal conditioning can be switched under software control such that: D1 - D2 FE n = 2 x --------------------D1 + D2 The error signal, FEn, is further processed by a Proportional Integral and Differential (PID) filter section. A Focus OK (FOK) flag is generated by means of the central aperture signal and an adjustable reference level. This signal is used to provide extra protection for Track-Loss (TL) generation, drop out detection and the focus start-up procedure.
handbook, full pagewidth
SATELLITE DIODE R1
SATELLITE DIODE R1
SATELLITE DIODE R1
D1 D3 D2
D2 D4
D1 D3
D1 D2 D3 D4
SATELLITE DIODE R2
SATELLITE DIODE R2
SATELLITE DIODE R2
single Foucault
astigmatic focus
double Foucault
MBG422
Fig.5 Detector arrangement.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
7.3.2 Focus control
SAA7348GP
switched off, applied only to focus control, or applied to both focus and radial controls under software control. The actions of the circuit can be monitored on the DEFO pin (active HIGH). An external defect detector can be added by removing the connection between DEFO and DEFI (normal operation) and inserting the necessary circuitry. 7.3.8 DRIVER INTERFACE
The SAA7348 performs the following focus servo function: * Focus start-up * Focus position control loop * Drop-out detection * Focus loss detection and fast restart * Focus loop gain switching * Focus automatic gain control loop. 7.3.3 RADIAL CONTROL
The SAA7348 performs the following radial servo functions: * Level initialization * Radial position control loop * Sledge control * Tracking control * Access with or without track loss information * Radial automatic gain control loop. 7.3.4 OFF-TRACK COUNTING
The control signals (pins RA, FO and SL) for the mechanism actuators are pulse density modulated. The modulating frequency can be set to either servo clock servo clock ----------------------------- or ----------------------------- MHz. An analog representation 8 4 of the output signals can be generated by connecting a first order low-pass filter to the outputs. During reset (i.e. RST pin held HIGH) the RA, FO and SL pins are high impedance. 7.3.9 LASER INTERFACE
The track position signal (TPI) is a flag used to indicate whether the radial spot is positioned on the track with a margin of 0.25 of the track pitch. One of the following three counting states is selected: * Protected state * Slow counting state * Fast counting state. 7.3.5 OFF-TRACK DETECTION
The LDON pin (open-drain output) is used to turn the laser on and off. When the laser is on, the output is high impedance. The action of the LDON pin is controlled by the xtra_preset parameter; the pin is automatically driven if the focus control loop is active. 7.4 Subcode interface
There are two subcode interfaces: * One which conforms to "EIAJ CP-2401" (using SBSY, SFSY, RCK and SUB) and can be configured as either a 3- or 4-wire interface. The interface formats are illustrated in Fig.6. * An RS232 like format on SUBQW as illustrated in Fig.7. 200 The subcode sync word is formed by a pause of --------- s n minimum. Each subcode byte starts with a 1 followed by 7 bits (Q to W). The gap between bytes can vary 11.3 90 between ---------- and ----- s. Note that SUBQW is not n n valid in lock-to-disc mode (includes QLLV). The subcode data is also available at the EBU output (DOBM).
The Off-Track Detection (OTD) signal flags off-track conditions; the polarity of this signal is programmable. 7.3.6 SHOCK DETECTION
A shock detector can be switched on during normal track following. Within an adjustable frequency range, it detects whether disturbances in the radial spot relative to the track exceed a programmable level. Every time the Radial tracking Error (RE) exceeds this level, the radial control bandwidth is switched to twice its original bandwidth and the loop gain is increased by a factor of 4. 7.3.7 DEFECT DETECTION
A defect detection circuit is incorporated into the SAA7348. If a defect is detected, the circuit can hold all radial and focus controls. The defect detector can be 1997 Jul 11 15
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
handbook, full pagewidth
SF0
SF1
SF2
SF3
SF97
SF0
SF1
SBSY SFSY RCK P-W SUB EIAJ 4-wire subcode interface P-W P-W
SF0 SFSY RCK
SF1
SF2
SF3
SF97
SF0
SF1
P-W SUB
P-W
P-W
EIAJ 3-wire subcode interface
SFSY RCK P SUB Q R S T U V W
MBG410
Fig.6 EIAJ subcode (CD graphics) interface format.
200/n s min W96 1
11.3/n s Q1 R1 S1 T U1 V W1
11.3/n s min 90/n s max 1 Q2
MGK501
(1) n = disc speed.
Fig.7 Subcode format and timing on SUBQW pin.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
7.5 Digital output
SAA7348GP
* Data taken after concealment, mute and fade (can only be used for audio modes). 7.5.1 FORMAT
The AES/EBU signal on pin DOBM is in accordance with the format defined in "IEC 958". This signal is only available in the decoder's CLV modes if audio features are enabled (not in QCLV modes). Three different modes can be selected: * DOBM pin held LOW * Data taken before concealment, mute and fade (must always be used for CD-ROM modes) Table 3 32-bit digital audio output format BITS 0 to 3 4 to 7 4 8 to 27 28 29 30 31 note 1 not used; normally zero
The digital audio output consists of 32-bit words (`subframes') transmitted in bi-phasemark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384.
FUNCTION Sync Auxiliary Error flags Audio sample(2) Validity User flag(3) data(4)
DESCRIPTION
CFLG error and interpolation flags when selected by register A first 4 bits not used (always zero); two's complement; LSB = bit 12, MSB = bit 27 valid = logic 0 used for subcode data (Q to W) control bits and category code even parity for bits 4 to 30
Channel status(5) Parity bit Notes
1. The sync word is formed in violation of the bi-phase rule and, therefore, does not contain any data. Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations: a) Sync B: word contains left sample (start of a block, 384 words). b) Sync M: word contains left sample (no block start). c) Sync W: word contains right sample. 2. Left and right samples are transmitted alternately. 3. Audio samples are flagged (bit 28 = 1) if an error was detected but could not be corrected. This flag remains the same even if data is taken after concealment. 4. Subcode bits Q to W from the subcode section are transmitted via the user data bit. This data is asynchronous with the block rate. 5. The channel status bit is the same for both left and right words. Therefore, a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is shown in Table 4.
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Preliminary specification
All Compact Disc Engine (ACE)
Table 4 Channel status bit assignment BIT 0 to 3 4 to 7 8 to 15 28 and 29 DESCRIPTION
SAA7348GP
FUNCTION Control Reserved mode Category code Clock accuracy
copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has pre-emphasis always zero CD: bit 8 = logic 1, all other bits = logic 0 set by register A: 10 = class 1 crystal (<50 ppm) 00 = class 2 crystal (<1000 ppm) 01 = class 3 crystal (>1000 ppm)
Remaining 7.6 S2B interface
16 to 27 and 30 to 191 always zero - peak detector (measures highest audio level; absolute level for left and right channels; the 8 MSBs of each are output in the Q-channel data). * Mono output selection. Either channel can be selected to be output over both left and right channels. 7.7.1 SERIAL AUDIO DATA INTERFACE
This interface is in accordance with the "S2B Interface Description". It's a serial interface with a high level command set for controlling a CD-ROM engine. 7.7 Audio support
Audio support consists of several parts: * Serial data interface. * Deemphasis control (DEEM). This signal is HIGH if the subcode info of a track defines it to be recorded with deemphasis. * Kill control (KILL). This signal tests for digital silence in the right and left channel before the digital filter. The output is switched active LOW if silence has been detected for at least 250 ms, if mute is active, or in CD-ROM modes. * Output clock for BCC-DAC applications (DACCLK). * Oversampled output. The SAA7348 contains a 2 to 4 times oversampling IIR (Infinite Impulse-Response) filter, and a selectable deemphasis filter (if the de-emphasis signal is selected to come out of DEEM then the filter is bypassed; see Table 31). * Concealment, mute, attenuation and fade. In audio modes a 1-sample linear interpolator becomes active if a single sample is flagged as erroneous; left and right channels have independent interpolators. A digital level converter performs the following functions: - soft mute (signal reduced to 0 in a maximum of 128 steps) - full-scale (signal ramped back to 0 dB level) - attenuation (signal scaled by -12 dB) - fade (activates a 128 stage counter which allows the signal to be scaled up or down in 0.07 dB steps) The serial data interface can be switched between two modes: Philips I2S and the EIAJ format. In each case, the serial data is transferred through a 3-wire interface. The I2S signal contains three components: WCLK (word select), SCLK (serial clock) and DAC (serial data). The polarity of WCLK and of the data can be inverted. The oversampling frequency and format are selected as shown in Table 5. The serial data output is separate from the CD-ROM output. In CD-ROM mode the DAC serial data output pin will be muted. Table 5 Oversampling frequency select NUMBER OF BITS 18 18 16 EIAJ 18 18 18 16 16 16 SAMPLE FREQUENCY 4fs 2fs fs 4fs 2fs fs 4fs 2fs fs
MODE I2S
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Preliminary specification
All Compact Disc Engine (ACE)
7.8 CD-ROM support
SAA7348GP
supply pins. To ensure that the SAA7348 resets fully it is necessary to do one of the following: * Connect SELPLL to DSDEN (rather than VDD). This allows the internal clock multiplier to start immediately after reset. Note that the internal clocks are not guaranteed to operate at the correct frequencies for the first 200 s after reset. Note also that the operating speed of the microcontroller is reduced in Idle mode (and that baud rates change with the processor clock). * Connect SELPLL to an inverted reset signal. The internal clock multiplier starts after reset, but during Idle mode the microcontroller speed is normal. 7.10 External ROM support
The principle difference between the ACE and its predecessors with regard to CD-ROM support is the provision of a separate serial data pin, which removes the need for external components. The format can be I2S or EIAJ. 7.8.1 SERIAL CD-ROM DATA INTERFACE
The serial data signal contains three components: WCLK (word select), SCLK (serial clock) and DATA (serial data). The polarity of WCLK and of the data can be inverted. WCLK and SCLK are common with the audio serial data output. The VALID signal is used to flag errors in either the LSB or MSB of the 16-bit data word. 7.9 Reset
The RST pin on the SAA7348 is an active HIGH Schmitt trigger. For a valid reset, the signal should be HIGH for a period of 12 XTALI clock cycles, during which time the power supply must be within specification on all power
Since the ACE incorporates an 80C51 core it can, like any microcontroller, run a program from external ROM. The EA pin should be tied to VSS in this case. For security reasons, this pin is only sampled during reset, so a program cannot be run partly from external ROM. Signal relationships for external program execution are shown in Fig.8. Timing specification can be found in Table 6.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
Table 6 Timing specifications for external program memory search PARAMETER ALE pulse width address valid to ALE LOW address hold after ALE LOW ALE LOW to PSEN LOW PSEN pulse width PSEN LOW to valid instruction in input instruction hold after PSEN input instruction float after PSEN address to valid instruction in PSEN LOW to address float read pulse width write pulse width RD LOW to valid data in data hold after RD data float after RD ALE LOW to valid data in address to valid data in ALE LOW to RD or WR LOW address valid to RD or WR LOW data valid to WR transition data hold to WR RD LOW to address float RD or WR HIGH to ALE HIGH 60 15 21 25 80 - 0 - - - 170 170 - - 0 - - 80 115 20 20 - 20 MIN. - - - - - 65 - 30 130 6 - - 135 50 - 235 260 115 - - - 0 40
SAA7348GP
SYMBOL tLHLL tAVLL tLLAX tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH
MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
UNIT
In addition to external program memory, external RAM and I/O can be accessed. Timing relationships for an external data read are shown in Fig.9, and for an external data write in Fig.10.
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Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
handbook, full pagewidth
tLHLL ALE tAVLL tLLPL tPLPH tPLIV PSEN tLLAX tPXIZ tPXIX
tPLAZ LA0 to LA7 tAVIV A8 to A15
MGK502
Fig.8 Timing for an external program memory fetch.
handbook, full pagewidth
ALE tWHLH PSEN tLLDV tRLRH tLLWL RD tAVLL tLLAX tRHDZ
LA0 to LA7 tAVWL tAVDV A8 to A15
MGK503
Fig.9 Timing for an external data read.
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Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
handbook, full pagewidth
ALE tWHLH PSEN tLLWL WR tAVLL tLLAX tQVWX LA0 to LA7 tAVWL A0 to A15
MGK504
tWLWH
tWHQX
Fig.10 Timing for an external data write.
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Preliminary specification
All Compact Disc Engine (ACE)
8 MICROCONTROLLER INTERFACE
SAA7348GP
generates a single internal master clock from which all other clock signals are derived. Note that both the microcontroller and the servo are designed for a 50% duty factor input clock. For a 16x decoder speed, the internal master clock must be 67.7376 MHz (i.e. clock multiplier set to 8x). The 16.9344 MHz signal can be generated by setting the clock divider to 4, resulting in a standard 50% duty factor clock. For a 12x decoder speed, the internal master clock must be 50.8032 MHz (i.e. clock multiplier set to 6x). A divide factor of 3 will generate the 16.9344 MHz signal, resulting in a 66% duty factor clock. The clock divider values set by means of the CLKgen register are shown in Table 9.
This section describes the microcontroller application registers, the memory map, the decoder registers and the servo commands. 8.1 8.1.1 Microcontroller applications registers CLK GENERATE REGISTER (CLKgen)
The CLK generate register is used to select clock multiplier PLL frequencies and dividers and to switch the servo clock between single and double frequency. The register is byte addressable; R/W. The on-chip clock multiplier (programmable: 4x, 6x or 8x) allows an external 8.4672 MHz crystal to be used. This Table 7 7 CLK generate register (address 0X9EH) 6 5 CLKgen.5 4 clock_servohi
3 clock_seldiv2
2 clock_seldiv1
1 clock_selpll2
0 clock_selpll1
CLKgen.7 CLKgen.6 Table 8 BIT 7 6 5 4 3 2 1 0
Description of CLKgen bits SYMBOL CLKgen.7 CLKgen.6 CLKgen.5 clock_servohi clock_seldiv2 clock_seldiv1 clock_selpll2 clock_selpll1 these bits select the clock multiplier frequency; see Table 9 selects single or 2 x servo clock these bits select the clock divider for the 80C51 core and servo; see Table 9 not used DESCRIPTION
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Preliminary specification
All Compact Disc Engine (ACE)
Table 9 Divider selection REGISTER CLKgen BIT 0 0 0 1(1) 1(1) 1 0 1 0(1) 1(1) 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 0 1 0 1 SERVO CLOCK (MHz) 8.4672 16.9344 8.4672 16.9344 8.4672 16.9344 8.4672 16.9344
SAA7348GP
MASTER P CLOCK CLOCK (MHz) (MHz) 33.8688 50.8032 67.7376 33.8688 16.9344 16.9344 16.9344 16.9344
DIVIDE FACTOR 4 2 6 3 8 4 4 2
OVER-SPEED SERVO (%) 100 200 100 200 100 200 100 200
Note 1. The internal clock multiplier PLL operates at the same frequency for both these options.
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Preliminary specification
All Compact Disc Engine (ACE)
8.1.2 PORT SERVO REGISTER (PSR)
SAA7348GP
The Port Servo Register is the internal bus used to communicate with the servo. The register is bit addressable; R/W. The operation of the handshake bits used for serial communications with the servo is outlined in Table 12. Table 10 Port servo register (address 0XD8H to 0XDFH) 7 Tray_en 6 Tray_pwm 5 Srv_rdy 4 Srv_dacc 3 Srv_sild 2 Srv_sicl 1 Srv_sida 0 Srv_intreqn
Table 11 Description of PSR bits BIT 7 6 5 4 3 2 1 0 SYMBOL Tray_en Tray_pwm Srv_rdy Srv_dacc Srv_sild Srv_sicl Srv_sida Srv_intreqn ADDRESS 0XDFH 0XDEH 0XDDH 0XDCH 0XDBH 0XDAH 0XD9H 0XD8H signal to enable tray driver PWM signal to tray driver RDY; see Table 12 DAC; see Table 12 SILD SICL SIDA INTREQN DESCRIPTION
Table 12 Servo serial communication handshake signals DAC 0 0 1 1 RDY 0 1 0 1 DESCRIPTION transmit register full; the microcontroller can read a byte or send a new command idle state, transmit register empty; the microcontroller can transmit a parameter relating to the new command received one byte, waiting for EOT receive register full
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Preliminary specification
All Compact Disc Engine (ACE)
8.1.3 SERVO CONTROL REGISTER (SCR)
SAA7348GP
The Servo Control Register is used for reading and writing internal control signals. The register is byte addressable; R/W. Table 13 Servo control register (address 0XD9H) 7 Srv_frc_flock 6 Srv_frc_lock 5 Srv_otd 4 Srv_da 3 Srv_cl 2 Srv_rab 1 Srv_startup 0 Serv_halt
Table 14 Description of SCR bits BIT 7 6 5 4 3 2 1 0 SYMBOL Srv_frc_lock Srv_otd Srv_da Srv_cl Srv_rab Srv_startup Serv_halt DESCRIPTION force_lock; a HIGH indicates frequency lock OTD controller: off-track signal generated by the controller input for the OTD multiplexer; a HIGH indicates laser is off track DA (used only with direct decoder communication) CL (used only with direct decoder communication) RAB (used only with direct decoder communication) 16 kHz pulse (start new servo processor execution sequence); pulse is latched; latch is cleared by a write operation servo halt; halts servo processor execution Srv_frc_flock force_flock: coarse PLL lock indicator control; a HIGH indicates 6% of disc speed
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
8.1.4 SERVO STATUS REGISTER (STR)
SAA7348GP
The Servo Status Register holds high level status information on the servo system. The information is latched into a register and cleared whenever the register is read. This information could be a trigger to initiate a recovery. The register is byte addressable; read only. Table 15 Servo status register (address 0XE9H) 7 Srv_tl1 6 Srv_tl0 5 Srv_shock 4 Srv_hf_present 3 Srv_FIFO_ov 2 Srv_fock 1 Srv_otd_inp 0 Srv_subc
Table 16 Description of STR bits BIT 7 6 5 4 3 2 1 0 SYMBOL Srv_tl1 Srv_tl0 Srv_shock internal servo signal; see Table 17 internal servo signal; see Table 17 shock: decoder status signal; Motstart2 + PLL_phase_lock + Motor-ov + FOCOK + OTD FIFO_OV: decoder status signal; FIFO overflow occurred FOCOK: servo output signal; focus OK/OK OTD: servo output signal; laser spot on/off track subcode found: decoder status signal; subcode present in servo buffer DESCRIPTION
Srv_hf_present HF_present: internal decoder signal; indicates if laser spot is in a recorded area Srv_FIFO_ov Srv_fock Srv_otd_inp Srv_subc
The Srv_tl0 and Srv_tl1 signals can be used to determine in which direction the servo is counting during a jump execution. Table 17 Servo jump modes Srv_tl1 0 0 1 1 Srv_tl0 0 1 0 1 protected mode fast jump_1 slow jump fast jump_2 DESCRIPTION
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Preliminary specification
All Compact Disc Engine (ACE)
8.1.5 MOTOR OUTPUT QCLV REGISTER (MOQ; address 0XF2H and 0XF3H)
SAA7348GP
The Motor Output QCLV register holds the sixteen bits of the filtered (-3 dB, 300 Hz) motor error signal. This signal is updated at a frequency of 16.537 kHz. Address 0XF3H holds the eight most significant bits, address 0XF2H the eight least significant bits. Refreshing rule: if the low byte is read, the high byte is locked to avoid mixing up two successive samples. If the high byte has been read, the low byte will be refreshed. The register is byte addressable; read only. 8.1.6 P3 REGISTER
The P3 register is used in the same way as in the standard 80C51. It contains a second UART, however, whose input and output pins are RXD1 and TXD1 respectively. Direction control is by DDROUT3 (SFR address 0XFD; see Table 25 and Section 8.1.12). The register is bit addressable; R/W. Table 18 P3 register (address 0XB0H to 0XB7H) 7 WRN 6 RDN 5 TXD1 4 RXD1 3 INT1 2 INT0 1 TXD0 0 RXD0
Table 19 Description of P3 register bits BIT 7 6 5 4 3 2 1 0 SYMBOL WRN RDN TXD1 RXD1 INT1 INT0 TXD0 RXD0 ADDRESS 0XB7H 0XB6H 0XB5H 0XB4H 0XB3H 0XB2H 0XB1H 0XB0H WRN WDN TXD1: serial buffer 1; transmit RXD1: serial buffer 1; receive INT1: external Interrupt 1 INT0: external Interrupt 0 TXD0: serial buffer 0; transmit RXD0: serial buffer 0; receive DESCRIPTION
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Preliminary specification
All Compact Disc Engine (ACE)
8.1.7 DECODER STATUS REGISTER (DSR)
SAA7348GP
The decoder status register provides decoder status information. The register is byte addressable; read only. Table 20 Decoder status register (address 0XEBH) 7 6 5 4 3 2 1 0
Decoder_stat.7 TX_full Dec_motov Dec_pll_flock Dec_pll_lock Dec_motstop Dec_motstart_2 Dec_motstart_1 Table 21 Description of DSR bits BIT 7 6 5 4 3 2 1 0 SYMBOL Decoder_stat.7 TX_full Dec_motov Dec_pll_flock Dec_pll_lock Dec_motstop Dec_motstart_2 Dec_motstart_1 - communication buffer to decoder is full motor-overflow: decoder status signal; motor output saturates PLL_flock: decoder internal signal; can be forced by P PLL_lock: decoder internal signal; can be forced by P motstop: decoder status signal; speed <12% motstart 2: decoder status signal; speed >50% motstart 1: decoder status signal; speed >75% DESCRIPTION
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Preliminary specification
All Compact Disc Engine (ACE)
8.1.8 MOTOR SETPOINT REGISTER (MSR; address 0XF9H)
SAA7348GP
for setpoint/speed values. Note that these are measured values. They were measured using the motor control bread board. This bread board was hooked onto a ROM 65000 loader 12.66 application. The filter in the config control (Cnf_filter) was switched off. A motor gain of 5 was used. The register is byte addressable; R/W.
The motor setpoint register is used to set the speed of the motor in Quasi CLV mode. QCLV motor control is switched off by making the setpoint equal 00100000. See Table 22 Table 22 Speed measurements SFR SETPOINT 00100000 00100010 00100011 00100101 00100111 00101000 00101010 00101100 00101101 00101111 00110000 00110010 00110011 00110101 00110111 00111000 00101010 00111100 00111110 00111111 01000000 01000010 01000011 01000101 01000111 01001001 01001011 01001100 01001110 01001111 01010001 01010010 MEASURED SPEED 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9
SFR SETPOINT 01010100 01010110 01010111 01011001 01011011 01011100 01011110 01011111 01100001 01100010 01100100 01100110 01100111 01101001 01101011 01101100 01101110 01101111 01110001 01110010 01110100 01110110 01110111 01111001 01111011 01111100 01111110 10000000 01111111 10000001 10000011 10000100
MEASURED SPEED 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.7 7.8 7.9 8.0
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Preliminary specification
All Compact Disc Engine (ACE)
8.1.9 MOTOR GAIN QCLV REGISTER (address 0XFAH)
SAA7348GP
Table 23 for values). The actual gain depends on the filter in the config register (Cnf_filter). If the filtering is switched on, the gain is reduced by a factor of 8. The register is byte addressable; R/W.
The motor_gain_QCLV register is used to set the gain of the motor control signal. It can be used in quasi as well as in CLV mode. Only the 6 least significant bits are used (see Table 23 Loop gain GAIN SFR SETTING FILTER ON 00000000 00111111 00111110 00111101 00111100 00111011 00111010 00111001 00111000 00110111 00110110 00110101 00110100 00110011 00110010 00110001 00110000 00101111 00101110 00101101 00101100 00101011 00101010 00101001 00101000 00100111 00100110 00100101 00100100 00100011 00100010 00100001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FILTER OFF 0.125 0.25 0.375 0.5 0.625 0.75 0.875 1 1.125 1.25 1.375 1.5 1.625 1.75 1.875 2 2.125 2.25 2.375 2.5 2.625 2.75 2.875 3 3.125 3.25 3.375 3.5 3.625 3.75 3.875 4
GAIN SFR SETTING FILTER ON 00100000 00011111 00011110 00011101 00011100 00011011 00011010 00011001 00011000 00010111 00010110 00010101 00010100 00010011 00010010 00010001 00010000 00001111 00001110 00001101 00001100 00001011 00001010 00001001 00001000 00000111 00000110 00000101 00000100 00000011 00000010 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 FILTER OFF 4.125 4.25 4.375 4.5 4.625 4.75 4.875 5 5.125 5.25 5.375 5.5 5.625 5.75 5.875 6 6.125 6.25 6.375 6.5 6.625 6.75 6.875 7 7.125 7.25 7.375 7.5 7.625 7.75 7.875
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
8.1.10 DATA DIRECTION REGISTERS (DDR0, DDR2 AND DDR3)
SAA7348GP
The data direction registers are used to control the direction of data flow at the port pins (P0, P2 and P3). DDR0 controls P0; DDR2 controls P2; DDR3 controls P3. A logic 0 written to a bit makes the relevant port an input port. A logic 1 makes it an output port. The register is byte addressable; R/W. Table 24 Data direction registers (address DDR0: 0XFBH; DDR2: 0XFCH; DDR3: 0XFDH); note 1 7 6 5 Srv_otd 4 Srv_da 3 Srv_cl 2 Srv_rab 1 Srv_startup 0 Serv_halt
Srv_frc_flock Srv_frc_lock
Table 25 Description of DDR bits BIT 7 6 5 4 3 2 1 0 SYMBOL DDROUTX7 controls direction of PX.7 DDROUTX6 controls direction of PX.6 DDROUTX5 controls direction of PX.5 DDROUTX4 controls direction of PX.4 DDROUTX3 controls direction of PX.3 DDROUTX2 controls direction of PX.2 DDROUTX1 controls direction of PX.1 DDROUTX0 controls direction of PX.0 DESCRIPTION(1)
Note to Tables 24 and 25 1. X = 0, 2 or 3, depending on register selected (DDR0, DDR2 or DDR3).
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Preliminary specification
All Compact Disc Engine (ACE)
8.1.11 CONFIGURATION CONTROL REGISTER (CCR)
SAA7348GP
The Config_cntrl register is used to control internal multiplexers. Note that the motor output configuration register in the decoder is used to choose between the decoder motor control and the QCLV motor control. The register is byte addressable; R/W. Table 26 Description of CCR bits (address 0XFEH) BIT POSITION(1) READ 7 6 WRITE 7 6 Config_cntrl.7 Cnf_dac_clk_sel not used master clock selects clock to DAC; Cnf_dac_clk_sel = 1: -------------------------------- ; 2 master clock Cnf_dac_clk_sel = 0: -------------------------------3 5 4 3 2 1 0 Note 1. Note that the function of bit positions 1, 2, 3, 4 and 5 depends on whether the register is being written to or read from. 1 5 4 3 2 0 Cnf_AGC_bypass AGC decoder bypass; Cnf_AGC_bypass = 1: bypass; Cnf_AGC_bypass = 0: use AGC Cnf_lock_over Cnf_uPotd Cnf_sign_mag Cnf_filter Cnf_dircom Lock_over_rule; Cnf_lock_over = 1: overrules the decoder signals force_lock, force_flock selects OTD input; Cnf_uPotd = 1: controller; Cnf_uPotd = 0: DSICS selects PWM output mode; Cnf_sign_mag = 1: sign magnitude; Cnf_sign_mag = 0: two's complement selects the filter in the QCLV motor control; Cnf_filter = 1: enable; Cnf_filter = 0: disable selects decoder communication mode; Cnf_dircom = 1: direct; Cnf_dircom = 0: indirect (via the servo)
SYMBOL
FUNCTION
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
8.1.12 A SECOND SERIAL INTERFACE
SAA7348GP
priority level. The new vector address of the interrupt could be 0033H. 8.1.13 MEMORY MAP ACCESS TO THE SERVO
A second serial interface is implemented using the following registers: * SCON2: 0XC0 * SBUF2: 0XC1. This is of course an interrupt function. Bit 6 of the IE register is used to enable this function. Bit 6 of the IP register is used to define this interrupt to the highest
Since the performance of a basic engine is largely determined by the subcode retrieval speed, fast access to the subcode buffer is desirable. The servo RAM is mapped onto the AUX RAM of the microcontroller. In this way it is possible to directly access the servo RAM registers; see Table 27.
Table 27 Servo memory map ADDRESS (HEX) 0X100 0X101 0X102 0X103 0X104 0X105 0X106 0X107 0X108 0X109 0X10A 0X10B 0X10C 0X10D 0X10E 0X10F 0X110 0X111 0X112 0X113 0X114 0X115 0X116 0X117 0X118 0X119 0X11A 0X11B 0X11C 0X11D 1997 Jul 11 focus_stat rad_stat mem_sledge1_hi offtrack_hi_rb offtrack_lo_rb mem_sledge1_lo rad_int_hi rad_int_lo rad_offset_hi rad_error_gain_mem_hi tpi_gain_hi focus_error_mem rad_error_mem speed_hi speed_lo focus_int_hi focus_int_lo drop_out_code foc_prop_mem FOCUS_PROP_MULT FOCUS_INT_GAIN RAMP_MEAN_VALUE slee_mult_mem RAMP_HEIGTH FE_LEVEL timer1 acc_stat_mem rad_prop_mult_mem rad_error_acc_mem 34 CONTENTS time_keeper ADDRESS (HEX) 0X11E 0X11F 0X120 0X121 0X122 0X123 0X124 0X125 0X126 0X127 0X128 0X129 0X12A 0X12B 0X12C 0X12D 0X12E 0X12F 0X130 0X131 0X132 0X133 0X134 0X135 0X136 0X137 0X138 0X139 0x13A 0x13B CONTENTS rad_int_gain_mem speed_mult_mem rad_offset_lo rad_error_gain_mem_lo tpi_gain_lo sp_mem_lo sp_mem_hi speed_setpoint tpi_signal_mem rad_ctrl_1_mem2 rad_ctrl_1_mem rad_ctrl_2_mem rad_gain_mem stack 5 stack 4 stack 3 stack 2 stack 1 stack 0 oldcom state_mult_mem mem_sledge2_lo mem_sledge2_h RAMP_GAIN slede_mult_mem2 FAST_SPEED mem_sledge2_lo_lo gain_filter2_mem_lo gain_filter2_mem_hi gain_filter1_mem
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
ADDRESS (HEX) 0x13C 0x13D 0x13E 0x13F 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14A 0x14B 0x14C 0x14D 0x14E 0x14F 0x150 0x151 0x152 0x153 0x154 0x155 0x156 0x157 0x158 0x159 0x15A 0x15B 0x15C 0x15D
CONTENTS low_gain_mem gain_drempel_mem rad_ctrl_1_mem3 focus_int_mem1 interruptreg cd6statmem HiState MotorStatTime mem_sledge1_drempel_lo mem_sledge1_drempel_hi sledge_pulse_mem sledge_time_ou speed_drempel_mem hold_mult_mem xtra_preset cd6subadr cd6cmd1 cd6cmd2 asec asecold aframe aframemeold playwatchtimer interruptmask playwatchtimer trackcount1 timer2 jumpwatchtime sledge_long_brake radwatchstat sledge_power_mem rad_mem_part1 StateTimerHi StateTimerLo
ADDRESS (HEX) 0x15E 0x15F 0x160 0x161 0x162 0x163 0x164 0x165 0x166 0x167 0x168 0x169 0x16A 0x16B 0x16C 0x16D 0x16E 0x16F 0x170 0x171 0x172 0x173 0x174 0x175 0x176 0x177 0x178 0x179 0x17A 0x17B 0x17C 0x17D 0x17E 0x17F
CONTENTS FocusStartTime MotorStartTime1 MotorStartTime2 RadInitTime BrakeTime RadialStartStat sledge_pulse_height focus_inject radial_inject detphase oscinc injectlevel1 injectlevel2 osc agcgainmem agcgainlo focus_offset inject_lo offtrack_hi oftrack_lo not used not used subcode byte 0 subcode byte 1 subcode byte 2 subcode byte 3 subcode byte 4 subcode byte 5 subcode byte 6 subcode byte 7 subcode byte 8 subcode byte 9 peak level left peak level right
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
8.1.14 DIGITAL PLL REGISTERS
SAA7348GP
The behaviour of the digital PLL can be monitored and controlled using the following registers: 1. PLL Frequency Register (address 0XECH): This register holds the 8 MSBs of the PLL frequency. The register is byte addressable; read only. 2. PLL DC Offset Register (address 0XEDH): This register holds the 8-bit asymmetry signal in two's complement form. The register is byte addressable; read only. 3. PLL Jitter Register (address 0XEE): This register holds the 8 MSBs of the 10 jitter bits. The register is byte addressable; read only. 4. PLL Int Inp Register (address 0XFF): Presets the 8 MSBs of the PLL frequency to a certain value. The register is byte addressable; R/W.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
8.1.15 DIV17 REGISTER (address 0X9FH)
SAA7348GP
This register can be used to generate the serial communication baud rate. If this method is chosen, the baud rate will be 62259 x P. The 5 LSBs of DIV17 hold the value of P. The 2 MSBs connect this baud rate generator to UART 1 or UART 2 (see Table 28). The register is byte addressable; R/W. Table 28 Baud rate to UART connection BIT 7 0 0 1 1 BIT 6 0 1 0 1 baud rate generator not selected select baud rate generator only for UART1 select baud rate generator only for UART2 select baud rate generator for UART1 and UART2 DESCRIPTION
Of course in ACE it is still possible to use timers 1 and 2 to generate the baud rate. Table 29 provides an overview of how various baud rates can be generated using timer 1, timer 2, and DIV17. Table 29 Baud rate selection, timer based; note 1 BAUD RATE kBAUD 1411.20 996.14 529.20 498.07 373.55 264.60 249.04 186.78 124.52 88.20 66.15 62.26 44.10 33.08 9.80 Note 1. X = don't care. PCLK (MHz) 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 MODE 0 X 2 X X 2 X X X 1 1 X 1 1 1 SMOD X 1 1 1 1 0 1 1 1 1 X 1 0 X 1 RELOAD TIMER 1 X X X X X X X X X 0XFF X X 0XFF X 0XF7 RELOAD TIMER 2 X X X X X X X X X X 0XFFF0 X X 0XFFE8 X DIV17 (ACE) X 16 X 8 6 X 4 3 2 X X 1 X X X
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
8.2 Memory map
SAA7348GP
Table 30 Memory map ADDRESS(1) LOWER 0 1 2 3 4 5 6 7 8 9 A B C D E F Note 1. For example, hex address A8 = IE. PCON TCON TMOD TL0 TL1 TH0 TH1 CLKgen DIV17 SCON1 SBUF IE RSV RSV IP RSV T2CON T2MOD RCAP2L RCAP2H TL2 TH2 DSR PLLFREQ PLLOFS PLLJITT PSR SCR RSV SSR RSV MOTSETP MOTGAIN DDR0 DDR2 DDR3 CONFIG PLLINT 8 PO SP DPL DPH RSV 9 P1 A P2 B P3 UPPER C SCON2 SBUF2 MOTQCLVL MOTQCLVH D PSW E ACC F B
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
8.3 Summary of the functions controlled by decoder registers 0 to F
SAA7348GP
The decoder uses 16 programmable registers, accessible under internal microcontroller control. The addresses of these registers are given in Table 31, along with a summary of the functions performed. The INITIAL column shows the power-on reset state. Table 31 Decoder Registers 0 to F REGISTER 0 (Fade and attenuation) ADDRESS 0000 DATA X000 X01X X001 X100 X101 0XXX 1XXX 1 (Motor mode) 0001 X000 X001 X010 X011 X100 X101 X111 X110 1XXX 0XXX 2 (Status control) 0010 0000 0001 0010 0011 010X 011X 1X00 1X01 1X10 1X11 mute attenuate full scale step down step up DACCLK operating DACCLK 3-stated motor off mode motor brake mode 1 motor brake mode 2 motor start mode 1 motor start mode 2 motor jump mode motor play mode motor jump mode 1 anti-windup active anti-windup off status = SUBQREADY-I status = MOTSTART1 status = MOTSTART2 status = MOTSTOP status = PLL lock status = MOTOR-OV status = FIFO overflow status = shock detect status = latched shock detect status = latched shock detect reset FUNCTION INITIAL(1) reset - - - - - reset reset - - - - - - - - reset reset - - - - - - - - -
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
REGISTER 3 (DAC output)
ADDRESS 0011
DATA 1010 1011 110X 1111 1110 000X 0011 0010 010X 0111 0110
FUNCTION I2S-bus; CD-ROM mode EIAJ; CD-ROM mode I2S-bus; 18-bit; 4fs mode I2S-bus; 18-bit; 2fs mode I2S-bus; 16-bit; fs mode EIAJ; 16-bit; 4fs EAIJ; 16-bit; 2fs EIAJ; 16-bit; fs EIAJ; 18-bit; 4fs EIAJ; 18-bit; 2fs EIAJ; 18-bit; fs motor gain G = 3.2 motor gain G = 4.0 motor gain G = 6.4 motor gain G = 8.0 motor gain G = 12.8 motor gain G = 16.0 motor gain G = 25.6 motor gain G = 32.0 new motor control standard CD6 motor control motor f4 = 0.5 x n Hz motor f4 = 0.7 x n Hz motor f4 = 1.4 x n Hz motor f4 = 2.8 x n Hz motor f3 = 0.85 x n Hz motor f3 = 1.71 x n Hz motor f3 = 3.42 x n Hz motor power maximum 37% motor power maximum 50% motor power maximum 75% motor power maximum 100% MOTOS, MOTOV pins 3-state motor PWM mode motor PDM mode motor CDV mode
INITIAL(1) - - reset - - - - - - - - reset - - - - - - - reset - reset - - - reset - - reset - - - reset - - -
4 (Motor gain)
0100
X000 X001 X010 X011 X100 X101 X110 X111 0XXX 1XXX
5 (Motor bandwidth)
0101
XX00 XX01 XX10 XX11 00XX 01XX 10XX
6 (Motor output configuration)
0110
XX00 XX01 XX10 XX11 00XX 01XX 10XX 11XX
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
REGISTER 7 (DAC output control)
ADDRESS 0111
DATA xxx0 xxx1 xx0x xx1x 11xx 10xx 01xx 00xx
FUNCTION DAC data normal value DAC data inverted value left channel first at DAC (WCLK normal) right channel first at DAC (WCLK inverted) stereo output at DAC left mono out at DAC right mono out at DAC both DAC channels killed see Table 32
INITIAL(1) reset - reset - reset - - -
8 (PLL loop filter bandwidth) 9 (PLL equalization) 1001 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 A (EBU output) 1010 xx0x xx1x x1x1 x0x1 x0x0 x1x0 0xxx 1xxx
equalization = -60 ns equalization = -45 ns equalization = -30 ns equalization = -15 ns equalization = 0 ns equalization = 15 ns equalization = 30 ns equalization = 45 ns equalization = 60 ns equalization = 75 ns equalization = 90 ns equalization = 105 ns equalization = 120 ns equalization = 135 ns equalization = 150 ns equalization = 165 ns DOBM data before concealment DOBM data after concealment and fade DOBM off; output LOW class 1 crystal (<50 ppm) class 2 crystal (<1000 ppm) class 3 crystal (>1000 ppm) flags to DOBM off flags to DOBM on
- - - - reset - - - - - - - - - - - - reset - - reset reset -
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
REGISTER B (Speed control)
ADDRESS 1011
DATA x0xx x1xx 0xxx 1xxx xx00 xx10 xx11
FUNCTION 33.8688 MHz crystal present, or 8.4672 MHz crystal with SELPLL set HIGH 16.9344 MHz crystal present single speed mode (if register E = 0xxx) four times speed mode (if register E = 1xxx); note 2 double speed mode (if register E = 0xxx) eight times speed mode (if register E = 1xxx); note 2 standby 1: `CD-STOP' mode standby 2: `CD-PAUSE' mode operating mode 255 112 slicer bandwidth --------- or --------- Hz n n 112 56 slicer bandwidth --------- or ----- Hz n n 27 13 slicer bandwidth ----- or ----- Hz n n digital equalizer enabled digital equalizer disabled AGC active AGC inactive (on hold) subcode channels Q-W at SUBQW SUBQW = 0 SUBQW = 1 de-emphasis signal at DEEM, no internal de-emphasis filter DEEM = 0 DEEM = 1 bit controls operating speed mode, see register B audio features disabled audio features enabled lock-to-disc mode disabled lock-to-disc mode enabled low-stop = 0; motor brakes to 12% low-stop = 1; motor brakes to 6%
INITIAL(1) reset - reset - reset - - - - reset - reset reset - - - reset - - reset reset - reset reset - reset -
C (Data slicer and AGC control)
1100
1xxx 01xx 00xx xx0x xx1x xxx0 xxx1
D (Versatile pins interface)
1101
xx01 xx10 xx11 01xx 10xx 11xx
E
1110
0xxx x0xx x1xx xx0x xx1x xxx0 xxx1
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
REGISTER F (Subcode interface)
ADDRESS 1111
DATA x0xx x1xx 0xxx 1xxx xx10 xx10 subcode interface off subcode interface on 4-wire subcode 3-wire subcode
FUNCTION
INITIAL(1) reset - reset - - -
decrease AGC gain 1 step, when AGC off (register C) increase AGC gain 1 step, when AGC off (register C)
Notes 1. The initial column shows the power-on reset state. 2. Speed can be set to (1.5x, 3x, 6x and 12x) or (2x, 4x, 8x and 16x) via the microcontroller application register CLKgen. Table 32 Loop filter bandwidth FUNCTION REGISTER ADDRESS DATA LOOP BANDWIDTH (Hz) 1640 x n 3279 x n 6560 x n 1640 x n 3279 x n 6560 x n 1640 x n 3279 x n 6560 x n 1640 x n 3279 x n 6560 x n INTERNAL BANDWIDTH (Hz) 525 x n 263 x n 131 x n 1050 x n 525 x n 263 x n 2101 x n 1050 x n 525 x n 4200 x n 2101 x n 1050 x n LOW-PASS BANDWIDTH (Hz) 8400 x n 16800 x n 33600 x n 8400 x n 16800 x n 33600 x n 8400 x n 16800 x n 33600 x n 8400 x n 16800 x n 33600 x n INITIAL(1)
8 (PLL loop filter bandwidth)
1000
0000 0001 0010 0100 0101 0110 1000 1001 1010 1100 1101 1110
- - - - - - - reset - - - -
Note 1. The initial column shows the power-on reset state.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
8.4 Summary of servo commands
SAA7348GP
The servo commands are listed in Table 33. Table 33 Servo commands COMMANDS Write commands Preset_Latch Write_focus_coefs1 Write_focus_coefs2 Write_focus_command Focus_gain_up Focus_gain_down Write_radial coefs Preset_init Radial_off Radial_init Short_jump Long_jump Steer_sledge Write_decoder_reg Write_parameter Read commands Read_status Read_aux_status Read_Q_subcode Read_hilevel_status 70H F0H 0H E0H up to 5 up to 3 up to 4 81H 17H 27H 33H 42H 62H 57H 93H C1H C1H C3H C5H B1H D1H A2H 1 7 7 3 2 2 7 3 1 1 3 5 1 1 2 1Ch 3Ch CODE BYTES PARAMETERS
up to 12
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
8.4.1 SUMMARY OF SERVO COMMAND PARAMETERS
SAA7348GP
Table 34 Servo command parameters PARAMETER foc_parm_1 RAM ADDRESS - AFFECTS focus PID POR VALUE - DETERMINES end of focus lead defect detector enabling OTD polarity focus low-pass focus error normalising focus lead length minimum light level focus integrator crossover frequency focus PID loop gain sensitivity of drop-out detector asymmetry of focus ramp p-p value of ramp voltage slope of ramp voltage minimum value of focus error initial value for RE_offset initial value for RE_gain initial value for sum_gain end of radial lead radial low-pass length of radial lead radial integrator crossover frequency radial loop gain filter during jump PI controller crossover frequencies jump pre-defined profile maximum speed in fast track mode electronic damping of radial actuator sledge bandwidth during jump max sledge distance allowed in fast actuator steered mode brake distance of sledge two's complement MSB of number of tracks to jump two's complement LSB of number of tracks to jump radial and sledge control voltage on sledge during long jump voltage on sledge when steered
foc_parm_2 foc_parm_3 foc_int foc_gain CA_drop ramp_offset ramp_height ramp_incr FE_start RE_offset RE_gain sum_gain rad_parm_play rad_pole_noise rad_length_lead rad_int rad_gain rad_parm_jump vel_parm1 vel_parm2 speed_thres act_sled brake_dist_max sledge_brake_dist offtrack_hi offtrack_lo rad_stat sledge_Umax sledge_Uout
- - 14H 15H 12H 16H 18H - 19H - - - 28H 29H 1CH 1EH 2AH 27H 1FH 32H 48H 49H 21H 58H - - - - -
focus PID focus PID focus PID focus PID focus PID focus ramp focus ramp focus ramp focus ramp radial initialization radial initialization radial initialization radial PID radial PID radial PID radial PID radial PID radial jump radial jump radial jump radial jump radial jump radial jump radial jump radial jump radial jump radial/sledge sledge sledge
- - - 70H - - - - - - - - - - - - 70H - - - - 00H - 7FH - - - - -
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
PARAMETER sledge_parm_1 sledge_parm_2
RAM ADDRESS 36H 17H
AFFECTS sledge sledge
POR VALUE - -
DETERMINES sledge integrator crossover frequency shock filter sledge low-pass frequencies sledge gain sledge operation mode control pulse width control pulse height defect detector setting shock detector operation radial on-track watchdog time radial jump watchdog time-out enable/disable automatic radial off feature VRH level setting enable/disable decoder interface decoder interface speed interrupt request polarity fast radial brake laser on/off RA, FO, SL PDM modulating frequency enable/disable fast brake fast jumping circuit on/off send commands to decoder enabled interrupts autosequencer control focus start time motorstart1 time motorstart2 time radial initialisation time brake time radial command byte AGC control frequency of injected signal phase shift of injected signal amplitude of signal injected amplitude of signal injected focus/radial gain
pulse_time pulse_height defect_parm shock_level playwatchtime jumpwatchtime wradcontrol chip_init
46H 64H - - 54H 57H 59H -
pulsed sledge pulsed sledge defect detector shock detector watchdog watchdog watchdog set-up
- - - - - - - -
xtra_preset
4AH
set-up
38H
deccmd interruptmask seq_state FocusStartTime MotorStartTime1 MotorStartTime2 RadialInitTime BrakeTime RadCmdByte osc_frequency detect_phase injectlevel1 injectlevel2 agc_gain
4DH 53H 42H 5EH 5FH 60H 61H 62H 63H 68H 67H 69H 6AH 6CH
decoder interface STATUS pin autosequencer autosequencer autosequencer autosequencer autosequencer autosequencer autosequencer focus/radial AGC focus/radial AGC focus/radial AGC focus/radial AGC focus/radial AGC
- - - - - - - - - - - - - -
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD(pads) VDDD(core) VDDA VI VO PARAMETER digital supply voltage for pad cells digital supply voltage for the core analog supply voltage input voltage (any input) output voltage (any output) between the analog and digital (core) supply voltages IO II(d) Tamb Tstg Ves output current (continuous) diode DC input current (continuous) operating ambient temperature storage temperature electrostatic handling note 4 note 5 Notes 1. All pad supply pins (VDDDn(pads)) must be connected externally to the same power supply. 2. All VSS pins must be connected to the same external voltage. CONDITIONS notes 1 and 2 notes 2 and 3 notes 2 and 3 MIN. -0.5 -0.5 -0.5 -0.5 -0.5 - - - 0 -55 -2000 -200
SAA7348GP
MAX. +6.5 +4.0 +4.0 VDD + 0.5 +6.5 0.25 20 20 70 +125 +2000 +200 V V V V V V
UNITS
VDDA-DDD(core) supply voltage difference
mA mA C C V V
3. All analog and digital core supply pins (VDDA and VDDDn(core)) must be connected externally to the same power supply. 4. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor with a rise time of 15 ns. 5. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
10 CHARACTERISTICS
SAA7348GP
10.1 General characteristics VDDD(pads) = 4.5 to 5.5 V; VDDD(core) = 3.0 to 3.6 V; VDDA = 3.0 to 3.6 V; VSS = 0; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supply VDDD(pads) VDDD(core) VDDA IDD digital supply voltage for pad cells digital supply voltage for the core analog supply voltage supply current n = 8 mode 4.5 3.0 3.0 - 5.0 3.3 3.3 90 5.5 3.6 3.6 - V V V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Servo analog section (VDDD(pads) = 5.0 V; VDDD(core) = 3.3 V; VDDA = 3.3 V; VSS = 0; Tamb = 25 C) PINS: D1, D2, D3, D4, S1, S2, VRH, IrefT, FTCL AND FTCH Cint IIrefT RIrefT ID IS(max) IIrefT RIrefT Icd Isd VIrefT VD1-D4, S1, S2 VGAP VRH tch(VRH) (THD+N)/S internal capacitor D1, D2, D3, D4, S1 and S2 input current for IrefT external resistor on IrefT input current for central diode input signal maximum input current for satellite diode input signal input current for IrefT external resistor on IrefT input current for central diode input signal input current for satellite diode input signal voltage on current input IrefT voltage on current inputs D1, D2, D3, D4, S1 and S2 band gap voltage HIGH level reference voltage charge time VRH buffer total harmonic distortion-plus-noise to signal ratio at 0 dB; note 5 note 4 fsys = 4.2336 MHz; notes 1 and 2 fsys = 4.2336 MHz; notes 1 and 2 fsys = 4.2336 MHz; notes 2 and 3 fsys = 4.2336 MHz; notes 2 and 3 fsys = 8.4672 MHz; notes 1 and 2 fsys = 8.4672 MHz; notes 1 and 2 fsys = 8.4672 MHz; notes 2 and 3 fsys = 8.4672 MHz; notes 2 and 3 100 1.99 202 3.97 1.99 3.97 101 7.94 3.97 - - - 0.5 - - - - - - - - - - - virtual VGAP virtual VSSA 1.2 - - -50 - 5.95 603 11.91 5.95 11.91 302 23.81 11.91 - - - 2.5 50 -45 pF A k A A A k A A V V V V ns dB
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
SYMBOL S/N PSRR Gtol G cs Voffset(FTC)
PARAMETER signal-to-noise ratio
CONDITIONS - -
MIN. 55 45 0 - 60 -
TYP. - -
MAX.
UNIT dB dB % % dB mV
power supply ripple rejection at note 6 VDDA gain tolerance variation of gain between channels channel separation comparator FTC offset notes 2 and 7
-12 - - -10
+12 2 - +10
Decoder analog front-end (VDDD(pads) = 5.0 V; VDDD(core) = 3.3 V; VDDA = 3.3 V; VSS = 0; Tamb = 25 C) PINS: MIDLAD, REFLCA, HFIN, REFHCA AND Iref fclk BAGC Voffset Gv(AGC) ADC clock frequency AGC bandwidth (-3 dB) total offset voltage AGC gain: range step Vi(AGC)(p-p)) Vi(ADC) THD AGC input signal range; peak-to-peak value input range ADC plus buffer total harmonic distortion fs = 5 MHz fs = 10 MHz fs = 18 MHz S/N Zin Digital inputs INPUT: DEFI; CMOS INPUT WITH PULL-DOWN VIL VIH Rpd(int) Ci Vth(r) Vth(f) Vhys Ci VIL VIH ILI Ci 1997 Jul 11 LOW-level input voltage HIGH-level input voltage internal pull-down resistance input capacitance switching threshold rising switching threshold falling hysteresis voltage input capacitance VI = 0 -0.3 0.7 x VDD - - - 0.2 x VDD - - -0.3 0.7 x VDD VI = 0 - VDD -10 - 49 - - 50 - - - 0.33 x VDD - - - - - 0.3 x VDD V VDD + 0.3 V - 10 k pF signal-to-noise ratio input impedance HFIN -4.4 - 0.4 - - - - - - - 1.1 - 1.4 -36 -30 -25 33 10 +12.1 - 2.3 - - - - - - dB dB V V dB dB dB dB k n = 16 n = 12/16 67 18/24 -7 - - 0 - - +7 MHz MHz lsb
Input: RST; CMOS input with hysteresis 0.8 x VDD V - - 10 V V pF
INPUTS: RCK AND SELPLL; CMOS INPUTS LOW-level input voltage HIGH-level input voltage input leakage current input capacitance 0.3 x VDD V VDD + 0.3 V +10 10 A pF
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
SYMBOL Digital output
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
OUTPUTS: TPWM, TEN, SUBQW, DSDEN, CLO, DEEM, DEFO AND OTD VOL VOH CL to(r) to(f) LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time 10% to 90% levels; CL = 20 pF 90% to 10% levels; CL = 20 pF IOL = 2 mA IOH = -2 mA 0 VDD - 0.4 - - - - - - 23 27 0.4 VDD 25 - - V V pF ns ns
Open drain outputs OUTPUTS: RP, FOK, CFLG, C2FAIL, FB, TL, KILL AND LDON; OPEN DRAIN OUTPUTS VOL IOL CL to(f) LOW-level output voltage LOW-level output current load capacitance output fall time 90% to 10% levels; CL = 20 pF IOL = +4 mA 0 - - - - - - 27 0.4 4 25 - V mA pF ns
3-state outputs OUTPUTS: DACCLK, VALID, DAC, DATA, WCLK, SCLK, MOTOS, MOTOV, RA, FO, SL, DOBM, SBSY, SFSY AND SUB VOL VOH CL to(r) to(f) ILI LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time 3-state leakage current 10% to 90% level; CL = 20 pF 90% to 10% levels; CL = 20 pF VI = 0 - VDD IOL = 4 mA IOH = -4 mA 0 VDD - 0.4 - - - -10 - - - 24 28 - 0.4 VDD 50 - - +10 V V pF ns ns A
Digital Input/Output INPUTS/OUTPUTS: PSEN, ALE AND EA; CMOS INPUT/OUTPUT WITH PULL-UP VIL VIH VOL VOH to(r) to(f) CL Ci Rpu LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage output rise time output fall time load capacitance input capacitance input pull-up resistance VI = 0 IOL = 2 mA IOH = -2 mA 10% to 90% levels; CL = 20 pF 90% to 10% levels; CL = 20 pF -0.3 0.7 x VDD 0 VDD - 0.4 - - - - - - - - - 24 28 - - 50 0.3 x VDD V VDD + 0.3 V 0.4 VDD - - 50 10 - V V ns ns pF pF k
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
SYMBOL
PARAMETER
CONDITIONS
MIN. -0.3 0.7 x VDD - - - - - 24 28 - - - - - - -
TYP.
MAX.
UNIT
INPUTS/OUTPUTS: AD0 TO AD7, A8 TO A15, RXD0, TXD0, INT0, INT1, RXD1, TXD1, WR AND RD VIL VIH VOL VOH IL to(r) to(f) CL Ci VIL VIH tIH ILI Ci fxtal gm(mutual) Gv CF Co Notes servo clock 1. fsys is always equivalent to ----------------------------- ; see Section 10.2. 2 2. Current input range (resistor range) can be extended by 25% (minimum and maximum) but gain tolerance in this region is 25%. 3. V GAP x C DAC I i ( max ) = ---------------------------------- for unipolar A/D converter. For D1, D2, D3 and D4, Cref = CDAC. For S1 and S2, R ext x C ref Cref = 0.5 x CDAC 4. Internal reference source with 32 different output voltages. Selection is made during a calibration period or via the serial interface. The values given are for an unloaded VRH. The output voltage V RH = 0.5 x 10 v = 0 to 31. 5. VRH = 2.5 V, measuring bandwidth: 200 Hz to 20 kHz, fi(ADC) = 1 kHz. 6. fripple = 1 kHz, Vripple = 0.5 V peak-to-peak. 7. Gain tolerance is determined by the accuracy of the external resistor Rext. 8. It is recommended that the series resistance of the crystal or ceramic resonator is 60 . 1997 Jul 11 51
v ---------44.4
LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage 3-state leakage current output rise time output fall time load capacitance input capacitance IOL = 2 mA IOH = -2 mA VIN = 0 - VDD 10% to 90% levels; CL = 20 pF 90% to 10% levels; CL = 20 pF
0.3 x VDD V VDD + 0.3 V 0.4 VDD +10 - - 50 10 V V A ns ns pF pF
0 VDD - 0.4 -10 - - - - -0.3 -2.0
INPUT: XTALI (EXTERNAL CLOCK) LOW-level input voltage HIGH-level input voltage input HIGH time input leakage current input capacitance relative to period +0.5 55 +10 10 V % A pF VDD + 0.3 V
45 -10 -
OUTPUT: XTALO crystal frequency mutual transconductance small signal voltage gain feedback capacitance output capacitance note 8 at 100 kHz AV = gm x RO 8 - - - - 8.4672 10 18 - - 35 - - 5 10 pF pF MHz mA/V
, where
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
10.2 Subcode interface timing characteristics VDDD(pads) = 4.5 to 5.5 V; VDDD(core) = 3.0 to 3.6 V; VDDA = 3.0 to 3.6 V; VSS = 0; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT
Subcode interface timing (single speed x n); note 1; see Fig.11 INPUT: RCK tclkH tclkL tr tf td(SFSY-RCK) input clock HIGH time input clock LOW time input clock rise time input clock fall time delay time SFSY to RCK 2 -n 2 -n - - 10 ----n 4 -n 4 -n - - - 6 -n 6 -n 80 ----n 80 ----n 20 ----n s s ns ns s
OUTPUTS: SBSY, SFSY AND SUB (CL = 20 pF) Tcy(block) tW(SBSY) Tcy(frame) tW(SFSY) tSFSYH tSFSYL td(SFSY-SUB) td(RCK-SUB) th(RCK-SUB) block cycle time SBSY pulse width frame cycle time SFSY pulse width (3-wire mode only) SFSY HIGH time SFSY LOW time delay time SFSY to SUB (P data) valid delay time RCK falling to SUB hold time RCK to SUB 12.0 ---------n - 122 --------n - - - - - - 13.3 ---------n - 136 --------n - - - - - - 14.7 ---------n 300 --------n 150 --------n 366 --------n 66 ----n 84 ----n 1 -n 0 0.7 ------n ms s s s s s s s s
Note 1. The subcode timing is directly related to the over-speed factor, n, in normal operating mode; n is replaced by the disc speed factor, d, in lock-to-disc mode.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
handbook, full pagewidth
tW(SBSY)
Tcy(block)
SBSY tSFSYH SFSY (4-wire mode) tW(SFSY) SFSY (3-wire mode) tSFSYL tcy(frame)
SFSY 0.8 V td(SFSY-RCK) tr tf VDD - 0.8 V RCK 0.8 V td(SFSY-SUB) th(RCK-SUB) td(RCK-SUB) VDD - 0.8 V SUB 0.8 V
MBG414
Fig.11 Subcode interface timing.
1997 Jul 11
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
10.3 I2S timing characteristics VDDD(pads) = 4.5 to 5.5 V; VDDD(core) = 3.0 to 3.6 V; VDDA = 3.0 to 3.6 V; VSS = 0; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I2S Timing (single speed x n); note 1; see Fig.12 CLOCK OUTPUT: SCLK (CL = 20 pF) Tcy(clk) output clock period sample rate = fs sample rate = 2fs sample rate = 4fs tclkH clock HIGH time sample rate = fs sample rate = 2fs sample rate = 4fs tclkL clock LOW time sample rate = fs sample rate = 2fs sample rate = 4fs OUTPUTS: WCLK, DATA, VALID AND DAC (CL = 20 pF) tsu set-up time sample rate = fs sample rate = 2fs sample rate = 4fs th hold time sample rate = fs sample rate = 2fs sample rate = 4fs Note 1. I2S timing is directly related to the over-speed factor, n, in normal operating mode; n is replaced by the disc speed factor, d, in lock-to-disc mode. 95/n 48/n 24/n 95/n 48/n 24/n - - - - - - - - - - - - ns ns ns ns ns ns - - - 166/n 83/n 42/n 166/n 83/n 42/n 472.4/n 236.2/n 118.1/n - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns
clock period Tcy(clk) tCLKL tCLKH VDD - 0.8 V SCLK 0.8 V th WCLK DATA DAC VALID tsu VDD - 0.8 V 0.8 V
MGK505
Fig.12 I2S Timing.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
11 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SAA7348GP
SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X A A2
Q A1 (A 3) Lp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.20 0.05 A2 1.5 1.3 A3 0.25 bp 0.28 0.16 c 0.18 0.12 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 Q 0.70 0.57 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 15.75 15.75
ISSUE DATE 95-12-19
1997 Jul 11
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
12 SOLDERING 12.1 Introduction
SAA7348GP
* A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 12.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 12.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed:
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
13 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7348GP
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 14 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
NOTES
SAA7348GP
1997 Jul 11
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Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
NOTES
SAA7348GP
1997 Jul 11
59
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657027/1200/01/pp60
Date of release: 1997 Jul 11
Document order number:
9397 750 02136

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